Data transmission is an important application of many integrated circuit devices. Data may be transmitted according to different transmission protocols, and may be transmitted as serial data or parallel data. If both ends of a serial link use the same reference clock signal (i.e., a synchronous receiver (RX) input clock signal), then the clock and data recovery (CDR) architecture can be relatively simple, and may require only a phase error circuit.
However, each end of a serial data transmission link may use a separate, uncorrelated reference clock. If the frequencies of the near-end and far-end reference clocks are different, then the phase error must change continuously. As the difference in reference clock frequencies increases, the phase error must change more quickly, impacting the data recovery performance. The more extreme the difference in frequency and speed of change of frequency between the two ends of the link, the more difficult it is for the receiver to correctly recover the data. Eventually, a frequency error circuit may be required to accommodate asynchronous inputs.
Independent modulation to reduce electro-magnetic interference (EMI), termed Spread Spectrum Clocking (SSC), continuously varies the frequency of a reference clock. If the variation at each end of the link is uncorrelated with the other end, extreme changes in relative phase and frequency at each end of the link may be created, making it difficult to recover data.